Improve High Performance Factor for Floating Point Srt Division

The execution performances of the Sweeney, Robertson, Tocher (SRT) division algorithm depend on two parameters: the radix and the redundancy factor. In this paper, a study of the effect of these parameters on the division performances is presented. At each iteration, the SRT algorithm performs a multiplication by the quotient digit .This last can be just a simple shift, if the digit is a power of two otherwise; the SRT iteration needs a multiplier. We propose, in this work, an approach to circumvent this multiplication by decomposing the quotient digit into two or three terms multiples of 2. Then, the multiplication is carried out by simple shifts and a carry save addition. The implementation of this approach on Vertex-II field-programmable gate-array (FPGA) circuits gives best performances than the approach which uses the embedded multipliers 18 x 18 bits. The iterations delays are operands sizes independent. The reduction tree delays are at most equivalent to the delay of two Vertex-II slices. This approach was tested for the 4, 8, and 16 radixes in the two cases of minimum and maximum redundancy factors. By this study, we conclude that the use of the radix-8 with a maximum redundancy factor gives the best performances by using our approach for the double precision computation of the SRT division. INTRODUCTION The design of fast dividers is an important issue in high-speed floating point computing because division accounts for a significant fraction of the total arithmetic operations. It has been shown in [1], that although the division and related functions seem to be relatively unimportant instructions, with about 3% of all floating -point instructions count. However, in term of latency, they play a much larger role than multiplication. As the performance gap widens between addition/subtraction, multiplication, and division, floating-point algorithms and applications have been slowly rewritten to avoid the use of division [2]. It is not the relatively infrequent use of division that makes it less studied, but the complexity of its algorithms and the corresponding design challenges that make it neglected. The implementation of floating -point units on fieldprogrammable gate arrays FPGAs) has been virtually impossible until recently. Now with the rapid increase of FPGA density and speed, it is becoming possible to implement high performances floating -point division on FPGAs. In this paper, we are concerned by the floating -point computation of Sweeney, Robertson, Tocher (SRT)division which is the most common algorithm of digit-recurrence division implemented in modern CPUs like Pentium and UltraSparc-64 processors [3]. Taking its name from the initials of Sweeney, Robertson, and Tocher, who developed the algorithm approximately at the same time.